As a new B.S.E.E. degree graduate from the University of California, Davis, in 1972, I started work at the Link Division of the Singer Company in Sunnyvale, California, working on visual flight simulation. My initial role at Link was designing and testing digital circuit boards for the visual simulation part of military, commercial, and space flight simulators. The first system we sold was for NASA to use on the Shuttle Mission Simulator. Electrically programmable read-only memories (ROMs or EPROMs in this case) were one of the latest technologies at the time available in 256-b (32 words x 8 b) and 1K-b (256 words x 4 b) sizes fast enough (5 MHz) for our applications. The team realized that these devices could become the basis for flexible and configurable control circuits. The logic to implement this control consisted of a number of EPROMs addressed in parallel with circuitry to enable selected external signals to modify the next address.
In the larger control programs, it would have become quite cumbersome, time consuming, and expensive to burn new EPROMs every time a change to the control code was needed. This caused us to develop an “EPROM simulator” capable of storing 256 words x 80-b-wide control programs in random access memory (RAM). The 256-word limit was due to the size depth of available static RAM memory chips fast enough for our simulator application. The 80-b width was consistent with the 80 columns on then-standard punched cards. This EPROM simulator was designed and built in parallel with the first logic control board so that the simulator would be available for the initial test of the control subsystem. Engineers would first develop a control flowchart on paper and then commit that flowchart to paper coding sheets that contained ones or zeros to be keypunched and verified. We had an old Honeywell computer with a punched card reader and paper tape punch. Our EPROM simulator was then equipped with a paper tape reader, and we were in business.
Because of available static RAM speeds at the time and the design of our simulator, cycle speeds were limited to about 1 MHz. This wasn’t full speed, but it was adequate to prove our control and subsystem design concepts. Connecting one of the simulator satellite modules to one of our new control logic boards required up to 20 small flat cables to be connected between the EPROM simulator and control board EPROM IC sockets. It took a fair amount of fiddling and finesse to get one of the simulator modules working reliably while connected to our system. Once solid, however, it remained so as long as it wasn’t disturbed or bumped.
Tools for control logic development have certainly evolved tremendously over the past 40+ years. We thought ourselves quite advanced and fortunate to have the facilities we did at the time. The alternatives would have proven both costly and time consuming. The development schedule was always our most ferocious enemy. Having even those primitive tools enabled the engineering teams to accomplish great things against aggressive schedules. The mission simulator only stayed on the first launch critical path for a short time.